M.E. VLSI Design
Two year P.G degree M.E VLSI design is established from the year 2010 with an intake of 18 and subsequently reached its maximum of 36 in the year 2011.
The Department has excellent infrastructure and faculty members with rich experience in both teaching and industry, committed for cause of quality education. The Department organizes workshops, seminars and invited talks from various experts.
Our curriculum is designed by Anna University. It helps our graduates become viable in a globally competitive work environment. The laboratories consist of all the latest equipments and soft wares to meet the dynamic changes in the curriculum. The passed out students are working in various reputed industries in India.
The Quality objectives of the college are defined, consistent with the Quality Policy of the institution and in measurable terms, so that review is possible to effect continuous improvement
- To achieve an overall result of 80% in each semester.
- To achieve a 90% result in each subjects.
- To enhance students through personality development programs.
- To provide counseling effectively
- To arrange staff training programmes in each semester
- To encourage the students to attend inter-college seminars
- To encourage the students to carry out their research work
- Wireless LAN Trainer Kit
- Texas Instruments DSP Kits/TMS320C31/50.
- Spartan 3e trainer kit.
- Digital Storage Oscilloscope
- ARM kit
- TANNER software
- MENTOR GRAPHICS
|Academic year||Details of seminars / Workshops / Conferences|
- 1)Efficient High Throughput Multi standard Transform Core Realization on Fpga.
- 2)QDR SRAM Design using Multi-Bit Flip-Flop.
- 3)A Neural Network Implementation of Hyperbolic Tangent Function Using Approximation Method
- 4)Performance Evaluation and Low-Power CRN Architecture Design Using Spectrum Sensing Technique
- 5)Low Power Design Methodology of down Sampler using Dual Gate MOSFET
- 6)Generation of Pseudo-Random Number by using well and Reseeding Method.
- 7)Efficient Algorithms and Architectures for Avoiding Side Channel Effect Using ECC
- 8)Modeling and Testing of Gate Oxide Shorts in SRAM and DRAM.
- 9)Integrated Type NAND Gate using CMOS Logic Gates.
- 10)Realization of Sequential Latching using Verilog HDL without Synchronization
- 11)Delay Measurement in Analog and Mixed Signal BIST by Using Sampling Head Technique.
- 12)VLSI Implementation of Error Detection and Correction Using Enhanced Low Density Parity Check (LDPC) Codes
- 13)Versatile Modified Booth Recorder in FAM Unit Using SMB Recording Techniques.
- 14)Power Efficient and Increase RNM of Single Bit line SRAM and DRAM.
- 15)An Analytical Model of High Efficiency Emulation Attacks in Cognitive Radio Network.
- 16)Optimization of Area and Power Using Graph Based Algorithm for Filter Design.
- 17)An Efficient VLSI Architecture Design for Advanced Multi standard Turbo Decoder
- 18)VLSI Architecture Design for Ai Based 1-D/2-D Daub-6 and Daub-12 Wavelet Filter Banks with Low Adder Count
- 19)Design of Double Tail Comparator for Low Power Application
- 20)Optimization of Low Voltage Charge Pump with Stacking Power Gating for low leakage in Circuits.
UNIVERSITY RANK HOLDERS
Ms.DURGADEVI-34TH RANK – (2012-14) BATCH